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URL:     http://vhdl.org/vi/vital/

Title:     VITAL (VHDL Initiative Towards ASIC Libraries)

Description:     The objectives summary is accelerate the development of sign-off quality ASIC macrocell simulation libraries written in VHDL by leveraging existing methodologies of model development.

Directory:     Science/Technology/Electronics/Design/Hardware_Description_Languages/VHDL

 
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