| Directory > Science > Technology > Electronics > Design > Verilog and VHDL Tools VHDL FAQ
General VHDL resource including and information on books, tutorials, commercial products, and a
FAQ.
http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html
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Calyptech Design Services
Offers ASIC and FPGA design and verification services, drivers and tools. Includes product and
service overview and PDF detailed product specifications available.
http://www.calyptech.com/
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Experimental Computing Laboratory
Includes papers, presentations, conference publications and SAVANT VHDL, a free VHDL analyser and
simulator. From University of Cincinnati.
http://www.ececs.uc.edu/~paw
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Cypress Warp Tools
VHDL and Verilog tools for use with the Cypress CPLD family.
http://www.cypress.com/pld/warp.html
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TimingTool - Online timing diagram editor
Free to use online timing diagram editor. Timing diagrams are saved in TDML format. Translators
from TDML to DXF, VHDL, and Verilog are also supplied.
http://www.timingtool.com/
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Time Rover
Provides tools for aiding Verilog development. Including The Temporal Rover for automatic
verification of protocols and Verilog Java PLI.
http://www.time-rover.com/
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Green Mountain
VHDL compilers and design environments, including Windows, DOS and Linux support.
http://www.gmvhdl.com/
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Verilog-AMS
The Verilog-AMS Technical Subcommittee has been created with the charter to develop, update and
promote analog and mixed signal extensions to the Verilog (IEEE-1364) language.
http://www.eda.org/verilog-ams/
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C Level Design
Offers a design and verification environment for C/C++ with synthesis to VHDL and Verilog code.
http://www.cleveldesign.com/
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Esperan
VHDL, Verilog and FPGA training courses held in the US, Europe and the UK.
http://www.esperan.com/
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eXsultation
Specialize in full turn-key, customer facility training programs in VHDL, Verilog,C++ modeling,
formal verification, and FPGA design.
http://www.exsultation.com/
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SynaptiCAD
Provides Verilog, VHDL, TDML, logic analyzer, pattern generator, and SPICE tools.
http://www.syncad.com/
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VIZEF
Provide graphical HDL tools for design and verification.
http://www.vizef.demon.co.uk/
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Translogic
EASE and EALE provide HDL aware entry tools, both graphical and text based. Also providing Linux
support.
http://www.translogiccorp.com/
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Synplicity
Logic synthesis and verification products for FPGA and ASIC designers.
http://www.synplicity.com/
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Symphony EDA
VHDL Simili a freeware VHDL compiler/simulator. It supports VHDL'93, Vital, and SDF. Support for
Altera, Atmel, Cypress and Xilinx.
http://www.symphonyeda.com/
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Sutherland HDL, Inc.
Provides Verilog HDL and Verilog PLI training workshops and consulting services.
http://www.sutherland-hdl.com/
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Saros
Offering a full suite of VHDL and Verilog design tools, from design-entry, simulation and synthesis
to verification and training.
http://www.saros.co.uk/
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The Hamburg VHDL Archive
A collection of public-domain or shareware, VHDL documentation, models, and tools.
http://tech-www.informatik.uni-hamburg.de/vhdl/vhdl.html
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Freeware Verilog & VHDL
This is the home page for a Freeware Verilog,VHDL and Analog Mixed Signal project (a.k.a. the
V-2000 project, still in its infancy).
http://www.v-ms.com/
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Verilog Dot Com
Verilog resources page. Includes FAQ, books and links. Also verilog aware Emacs add on.
http://www.verilog.com/
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iMODL
The iValidate toolset comprises ready-to-use functional verification tools and simulation models.
http://www.imodl.com/
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Exemplar Logic, Inc.
Provides LeonardoSpectrum which is a CPLD, FPGA and desktop ASIC synthesis solution.
http://www.exemplar.com/
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Doulus
Lots of VHDL and Verilog resources. Including PaceMaker Self-Teach software.
http://www.doulos.co.uk/
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CAST, Inc.
Tools for intellectual property (IP) management. Plus synthesizable cores and simulation models
using VHDL and Verilog.
http://www.cast-inc.com/
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Aldec
HDL design entry and simulation software for programmable logic designers.
http://www.aldec.com/
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Accolade Design Automation
VHDL design, simulation and synthesis tools.
http://www.acc-eda.com/
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Nova Engineering
Megafunctions are modular, DSP algorithms and functional blocks for custom use in PLD or ASIC
designs.
http://www.nova-eng.com/vhdl.html
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Sandstrom Engineering
HDL pre-synthesis tools which check code for synthesizability. Then suggest replacement code where
problems are found.
http://www.sandstrom.org/about.htm
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StateCAD
Automatic VHDL and Verilog code from graphical state machine and data flow logic.
http://www.statecad.com/
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Rajesh Verilog FAQ
General Verilog resource that includes a FAQ, tutorials, and commercial information.
http://www.angelfire.com/in/rajesh52/verilog.html
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